1. Field of the Invention
The present invention is directed to phase-locked loops such as are commonly used in mobile communications terminals and other radio frequency receivers.
2. Description of the Related Art
Wireless communications devices, whether one-way or two-way, such as televisions, radios, cellular phones, pagers, personal digital assistants or the like are increasingly common in modern society. However, the convenience and case of use associated with these devices is not something that happens easily or simply. Each device typically receives an incoming electromagnetic signal through an antenna at a frequency that propagates easily through the atmosphere but is not always easily processed by internal electronic components within the device, and certainly not understandable by human senses. To change the frequency of the incoming signal to a frequency that is more easily manipulated, most wireless devices include a heterodyne type receiver that xe2x80x9cmixesxe2x80x9d the incoming signal with synthesized frequencies to produce lower or xe2x80x9cintermediatexe2x80x9d frequency outputs that may then be manipulated. In such situations, the synthesized frequencies must typically be generated within very tight frequency tolerances to mix the incoming signals down to the desired intermediate frequencies properly. Additionally, the synthesized frequencies should have little or no noise associated therewith to avoid corrupting or distorting the signal more than necessary.
Frequency synthesis is typically achieved by the use of one or more phase-locked loops (PLLs) that include a resonator driven oscillator and circuitry to ensure that the synthesized frequency is at the desired operating frequency. The most common implementation of such a resonator is based on combinations of inductor and capacitor elements, printed transmission line elements on the Printed Circuit Board (PCB), dielectric resonators, or Surface Acoustic Wave oscillators. While the quality (Q) factors of these resonators are high and phase noise levels of oscillators built from them are low, the oscillators remain xe2x80x9coff chipxe2x80x9d components that cannot be integrated together on an Application Specific Integrated Circuit (ASIC). Further, these oscillators may comprise up to fifteen elements which take both up space on the PCB and add cost.
Another oscillator used in prior art PLLs is a ring oscillator. Such prior art ring oscillators, while well suited for incorporation into an ASIC, are not considered low noise oscillators because any noise that exists within the oscillator is exacerbated by each pass through the ring oscillator. Another, less common solution to the problem of generating a stable high frequency signal from an accurate and low noise low frequency signal is the use of a delay locked loop (DLL) architecture. However, DLLs are also poorly suited for use in mobile radio applications because the duty cycle of the compare signal must be exactly 50%. If the duty cycle is not exactly 50%, a reference spur appears in the edge combined output signal. These spurs are difficult to filter from the combined signal and detrimentally impact the output.
For the vast majority of receivers, the prior art PLLs are adequate to meet the needs of the device that incorporated the PLL. However, portable receivers, such as those found in mobile terminals, such as pagers, cellular telephones, personal digital assistants, and the like, arc subject to constraints not typically found in televisions, stereos or the like. Specifically, mobile terminals are under increasing pressure to decrease their cost and size. If the PLL, and specifically the oscillator of the PLL, could be integrated into an ASIC, both pressures can be addressed. Integration into an ASIC decreases component cost and makes the device ultimately easier to manufacture, again reducing cost. Integration also eliminates bulky, off chip components, freeing space on the PCB and generally reducing the size of the mobile terminal.
Thus, while low noise integrated oscillators are highly desirable for mobile terminals, the presently available devices have proven less than satisfactory. Resonators cannot be incorporated into ASICs; ring oscillators are too noisy; and DLLs are too frequency limiting. Thus, there remains a specific need for a low noise oscillator that can be incorporated into an ASIC. Such an low noise oscillator could be used for a wide variety of applications including without limitation frequency synthesis, frequency multipliers to accelerate clock speeds, pulse to synchronization, clean signal generation for transmission, FM and AM detection, and the like.
The improved low noise oscillator of the present invention operates by selectively opening a ring oscillator to insert a reference input. Preferably, this reference input is inserted once per period of the reference signal, thereby resetting any accumulated timing errors (e.g., phase noise) each period. The improved low noise oscillator may be best illustrated in the context of an improved phase-locked loop (PLL).
In preferred embodiments, the ring oscillator is placed within the PLL, functioning as a voltage controlled oscillator. As is customary in the prior art, the PLL receives a periodic reference signal from a reference oscillator, sometimes called the compare signal. However, unlike the ring oscillators of the prior art, the loop in the ring oscillator is opened immediately prior to the arrival of the compare signal edge. While the ring oscillator loop is open, the reference signal is fed to the initial inverter instead of the initial inverter of the ring oscillator receiving the output from the last inverter of the ring oscillator. Shortly thereafter, the ring oscillator loop is closed again, and the structure operates as a conventional PLL with a ring oscillator until the next reset. The switching of the ring oscillator input is preferably accomplished via a switch operable between a ring setting (loop back ring oscillator output) and a reset setting (reference signal as input). It is believed that switching the input as described restarts the ring oscillator with zero timing error and resets any previously accumulated timing error, thereby reducing phase noise. In preferred embodiments, this reset methodology operates only when the PLL is in a locked mode and large corrections to the output of the oscillator are not required.
By employing the improved ring oscillator control method, all the components of a phase-locked loop may be easily integrated into a single ASIC capable of producing very low phase noise signals, such as would be useful in a heterodyne receiver for telecommunications applications.